As illustrated in FIG. 1, a conventional MC includes a data bus, an instruction register IR, a programmable logic array PLA, a data register D, a stack pointer SP, accumlators A and B, temporary registers TRB and TRC, a programmable counter PC, a ROM, and a RAM.
The program counter specifies instructions stored in the ROM, the instructions being sequentially transmitted to the instruction register IR via the data bus.
The PLA includes control output lines connected to internal registers and memories, etc., decodes instruction data transmitted from the IR, and delivers control signals such as an EM (enable memory) signal, a WACC (write accumulator) signal, an EROM (enable read only memory) signal, and a WM (write memory) signal. Those control signals are to switch on and off the internal registers and the memories, and transfer the data stored in the RAM, accumulator, and ROM, etc., onto the data bus or write the data on the data bus in the RAM and accumulator, etc.
The ROM stores instruction codes constituting instructions shown in FIG. 2a and FIG. 2b for exmaple. An instruction "ADD A, #N", which is represented by an instruction code "1010, 1010" or "A, A", means that the contents stored in the accumulator A are added with #N, that is, the contents of the second byte, and then, a result of the addition is stored into the accumulator. An instruction "ADD A, M", which is represented by an instruction code "0110, 0101" or "6, 5", means that the contents stored in the accumulator A are added with the contents stored in the RAM, and then a result of the addition is stored into the accumulator.
The PLA 200 includes, as illustrated in FIG. 3a for example, a plurality of NAND decoders 1, precharge circuits 2, 3, and a sense amplifier 18. The NAND decoder 1 comprises enhancement FETs indicated by circles (0) as illustrated in FIG. 3b and depletion FETs indicated by crosses (x) as illustrated in FIG. 3c. The precharge FET 2 has its one terminal connected to one terminal of the NAND decoder 1 and its other terminal connected to ground. The precharge FET 3 has its one terminal connected to the other terminal of the NAND decoder 1 and its other terminal connected to a power supply V.sub.DD. Those precharge FETs 2, 3 further have their gates connected to precharge signal lines PRC, respectively.
In the following, operation of the PLA circuit shown in FIGS. 3a-3c will be described with reference to timing charts shown in FIGS. 6(a), (b). In a time interval T1 of a timing cycle in an interval M1 of a machine cycle, the control signal EROM opens the output gate of the ROM to fetch out the instruction code stored in the ROM onto the bus and the control signal WIR opens the input gate of the instruction register 30 to store the instruction code on the bus in the instruction register 100. When the instruction code fetched out from the instruction register IR 100 is "A, A", the NAND decoders 1 on decode lines L'1, L'3 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in a timing cycle interval T3 the control output signal EACC is generated on a control output signal line 4 via the AND gates 6, and in a timing cycle interval T4 the control output signal WACC is generated. Additionally, when the instruction code is "6, 5", the NAND decoders 1 located on decode lines L'2, L'4 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in the timing cycle interval T3 the control output signal ACC is generated on the control output signal line 4, and in a timing cycle interval T4 the control output signal WACC is generated. Here, the control signals such as EROM, WIR, PCUP, and the like illustrated in FIG. 1 are issued from a timing control circuit T/C.
Such a conventional PLA circuit however, has a problem that all instruction codes for an instruction must be decoded to generate the control signals necessary for the execution of the instruction. One instruction code generally requires four decode lines on the average, for example the instruction "A, A" requires the decode lines L'1, L'3, the instruction "6, 5" requires the decode lines L'2, L'4, L'5, . . . . That is, about 100 instructions require about 400 decode lines in all. If the width of a single decode line of the PLA circuit which is formed on a semiconductor chip is assumed to be 10 .mu.m upon integrating the PLA, the PLA has its entire width ranging from 4 to 7 mm and hence occupies a wide areas of the semiconductor chip, therefore requiring that the chip be large.
Such a PLA incorporated, in the MC must be tested to determine whether or not it is operates in a proper manner. Such a test is carried out two or three times during the last stage of the manufacture of semiconductors or during a process of packaging the semiconductors. A typical MC includes about 100 to 200 output lines 4 for the control signals issued from the PLA. However, those control signal output lines 4 are connected to input/output gates of various of registers included in the MC but are not connected to external output terminals. This does not allow a direct check on that any control signal is issued from the PLA. Accordingly, to test the existence of any short-circuit in the wiring in the PLA and that of any abnormal FET in the same, a MC program stored in the ROM is first executed in succession for every instruction. Then, contents in each register which is the object of an instruction, and contents in all registers other than that which is the object of each instruction are read out each time for their checks. It is thereby checked that decoding and execution control of the instructions are carried out correctly, and tested indirectly that the PLA is normal. When for example an instruction "MOV A, B" is given from the outside to the MC and executed, a check of the contents stored in an accumulator (ACC) and a temporary register B (TRB) is performed to confirm that the contents stored in the TRB have been moved into the ACC, and to check that there is no change in the contents stored in other registers and the like after fetching out those contents to the outside followed by execution of the instruction "MOV A, B". However, the aforementioned operation to test the PLA requires, a data check concerning internal circuits amounting to 1000 to 100000 steps using the tester, which substantially makes it impossible to achieve the complete test. In addition, since the tester must usually be employed for varieties of test excepting the aforementioned object, use of such an expensive tester over a long period of time makes uneconomical the associated device. Furthermore, a program for such a test is very complicated, requiring much labor for preparation thereof.
In view of the drawback of the prior art, it is an object of the present invention to reduce the absolute number of decode lines while retaining their same functions as in the prior art. It is another object of the invention to provide a test of short duration of whether or not all of the wiring in the programmable logic array circuit is operationally normal.